1. Field of the Invention
The present invention relates to an apparatus for processing a video signal for use in such a case where a graphic image such as a character and a pattern are displayed in superimposition on a video image of a continuous television signal or the like.
2. Description of the Prior Art
FIG. 1 is a block diagram showing a prior art apparatus for processing a video signal disclosed, for example, in Japanese Laid-open Patent Publication No. 60-136828. Referring to the figure, an input video signal VI is processed in a decoder 2 so that color signals are separated from it. The obtained color signals are digitized in an A/D converter 3 and stored in a first memory 4 as video image data in units of field or frame. Where, the first memory 4 includes a controlling circuit for controlling data input to and output from the memory. Meanwhile, a graphic image of characters, patterns, or the like is input through the use of a man-machine interface 5 and stored via a disc controller 8 in a disk 9 for storing graphic images. Further, contents, sequence, program, and the like of the display are input through the use of the man-machine interface 5 and stored in a program memory 7 for storing programs, and execution of such image displaying programs and the like are controlled by a CPU 6. A bus 10 as a program control channel is connected to interfaces for the parts which the CPU 6 needs to execute the programs A DMA bus 11 for transmitting graphic image data is connected to a second memory 12 for storing the graphic image data in units of field or frame. The video image data or the graphic image data selectively read from the first memory 4 or the second memory 12 respectively to a first bus 13 which is controlled by a bus controller 14, is delivered to an output unit 15 to convert into an output video signal VO and a required picture as the result of image processing is displayed on a display monitor 16.
Below will be described operation with reference to a conceptual drawing of FIG. 2 and an operating model drawing of FIG. 3. The input video signal VI continuously input to the apparatus is decoded and separated into color signals R, G, and B in the decoder 2 and these color signals are converted into digital signals in the A/D converter 3. Then, these digitized video signals are stored in the first memory 4. For example, an input video signal VI whose contents are as shown in a picture d of FIG. 2 is stored in the first memory 4 in real time.
On the other hand, graphic image data as shown in a picture e of FIG. 2 has been produced in the man-machine interface 5 and stored in the disk 9. The graphic image data is read according to an instruction from the CPU 6 and delivered to the DMA bus 11 through the disk controller 8. The delivered graphic image data is stored in the second memory 12 in units of field or frame. The first memory 4 and the second memory 12 output their data at the same scanning timing (speed). At this time, as shown in FIG. 3, a decision portion 23 judges whether or not there exists a transparent color portion P within the picture e of the graphic image data output from the second memory 12, and according to the result of the decision, turns on one of the switches 21 and 22 so that one of the data in the memory 4 and the memory 12 is selectively output to the first bus 13. More particularly, the decision portion 23, when the transparent color portion P of the graphic image data of the second memory 12 is encountered during the scanning, turns on the switch 21 and turns off the switch 22, so that the video image data from the first memory 4 is delivered to the first bus 13, and, when, conversely, any other portions than the transparent color portion P, turns off the switch 21 and turns on the switch 22 so that the graphic image data from the second memory 12 is delivered to the first bus 13. As a result, an output video signal VO corresponding to a picture f of FIG. 2 is output through the output unit 15, and thereby, the picture f formed by superimposing the graphic picture e upon the video picture d is displayed on the display monitor 16.
Further, in the apparatus of this sort, implementation of a variety of display techniques incorporating reducing (or enlarging) processing is necessary, and the data and control command signals (such as a reduction or enlargement ratio and a position of display) required in image processing are supplied from the CPU 6 through the bus 10.
Since the prior art apparatus for processing the video signal was structured as described above, the first and second memories 4 and 12 each require interfaces with both the bus 10 and the first bus 13, and the second memory 12 further requires an interface with the DMA bus 11. Therefore, there has been a problem that the hardware configuration becomes complex.
Further, when the picture f' of FIG. 4 is switched to the picture f" of FIG. 5, the timing of the switching between the graphic images is controlled by the DMA bus 11, while the timing of the switching between the video images is dependent on the command transmission speed of the CPU 6. Therefore, due to the difference between the timings of switching for both the images, there is produced, at the time of switching between different display contents, a temporal discrepancy between the switching of the video image and that of the graphic image. Thus, there has been another problem that the switching between the different displays cannot be performed smoothly.